Flyback Output Diode Placement – High Side or Return Path?

Hello Manjesh,

If you are using the InnoSwitch3-EP, then you should place it in the return path similar to the SR Fet.

This allows the FWD pin of the InnoSwitch to function as normal. Remember to short the SR pin of the InnoSwitch to ground if you are not going to use an SR FET.

You can also use this DER as a reference for a flyback design that does not use an SR FET.

DER: DER-901 - 125 W 2-Stage Boost and Isolated Flyback 3-Way Dimmable LED Ballast Using HiperPFS-4 and PowiGaN-Based LYTSwitch-6 | Power Integrations 

It uses the Lytswitch6 instead of the InnoSwitch3-EP, but it should give you the idea of what the secondary side of the circuit should look like.

Hi,

Thanks a lot for the information.

I also have a follow-up question:
If I use a diode instead of a synchronous FET, will the snubber values across the diode remain the same?

The design guide states:

“A snubber resistor of 10 Ω to 47 Ω may be used (higher resistance values will lead to a noticeable drop in efficiency). A capacitance value of 1 nF to 2.2 nF is adequate for most designs.”

Could you please confirm whether this applies when using a diode instead of a FET?

Thanks alot in advance

You will likely need to tune the snubber to optimize the voltage across the diode. Too much snubber will cause a drop in efficiency. Too little snubber will result in a high voltage spike that may endanger the rectifier. You will likely need to juggle the snubber R and C values for optimum performance.

Hi,
Thanks for the suggestions.

Just a follow-up question regarding the connection of the EMC capacitor (3.3nF, Y-cap) between the primary and secondary sides of a Flyback transformer:

 If i choose to place the diode on the return path, the EMC capacitor should be connected on the cathode of the diode as shown in the picture or the anode side of the diode?

The schematic I’m referring to is attached for context.

Regards
Manjesh
 

You should ground the Y capacitor on the side of the diode that doesn't move around - in this case, the  anode side.  Otherwise, you will have an unpleasant EMI surprise.

Hi,

Thank you very much for the information.

I have one follow-up question regarding insulation coordination.
Our flyback converter is required to comply with IEC 62109-1, specifically with reinforced insulation between primary and secondary.

Could you kindly confirm whether the InnoSwitch3-EP (INN3679C) meets the following requirements for my application?

Based on IEC 62109-1: Pollution degree 2

1. Impulse withstand voltage: ≥ 6 kV (Table 12)
2. Temporary overvoltage (peak/effective): 2.55 kV / 1.8 kV (Table 12)
3. Clearance: ≥ 5.5 mm (Table 13)
4. Creepage – Other parts: ≥ 14.2 mm (Table 14, insulation material 2. 600 > CTI ≥ 400;) i think innoswitch has CTI>600?
5. Creepage – PCB: ≥ 10 mm (Table 14)

We would appreciate your confirmation if this controller satisfies the above requirements.

Best regards,
 

A lot of what you ask will depend on the transformer design. Depending on the wattage output of the design, you may need to use flying leads on the secondary output, spaced away from the transformer body, to attain the proper creepage distance. These leads will need to be speced closely (or taped together) to reduce the parasitic inductance on the transformer secondary, which shows up as a a leakage equivalent on the primary side. The transformer should be shrouded with tape to avoid arcing to the core (power ferrites are, unfortunately, electrically conductive) for output ESD testing.

The InnoSwitch definitely meets the PCB creepage requirement. I'm not so sure about the requirement for impulse withstand voltage or the temporary overvoltage requirement.

We routinely test the part at 3000VAC from primary side pins to secondary side pins without issues.

Thank you for your honest opinion.

However, I went through the datasheet and the IEC 62109 requirement. in the datasheet it is mentioned in page 39 about the voltage tests. There it is mentioned it can withstand 10.4kV Impulse withstand test.
Even I am not sure about the Temperory overvoltage (Peak/effective). 

Is it anyway possible to check this information from your side? that would be perfect.

Regards,


 

Also, we have requirement of Hipot test of 3kVAC or 4.2kV dc for 60s (Type test) and 1.5kVAC or 2.1kVdc for 1s (production). Is this compatible with the innoswitch INN3679C. In the 1st sheet of datasheet, it says HiPOT tested but does not provide the values.

Could you please also confirm this?

Thanks alot

I would have to acually mount the part down on a sample board to test this. When I have time, I will try it.

Thanks alot. That would be perfect so that I can finalize my design. 

Also, I found one of the test report from the PI, it might be helpful.

That particlar report is not all that useful, as it uses a DC hipot voltage instead of AC.

I probably won't see the test board until Monday.

Hi, its alright. Please let me know when you are done with the test.
 

I looked into the test report and they seem like using AC voltage for the test. It has shown in the description as well as in the graph. Am I missing something here?

 

OK, I put together the test board, and it passed 60sec at 3kVAC (actually 3.01kV) and 1sec at 1.5kVAC (actually1.51kV, but that's splitting hairs...). I got the single beep of "PASS" on the hipot tester rather than the extended squeal of failure - a good sign, that...

Hi,
Thanks alot and that is more than enough information I wanted to have. Thanks alot for making these tests. Much appreciated. Now, I can qualify this part to be used for my application.
Have a great day
 

Hi again,

Back to the previouse question about secondary rectifier diode/Mosfet. I am finalize the circuit for the PCB prototype. I would like to keep Mosfet and the diode footprint to check both of them. I put up a 0 ohm series resistor to SR pin when im using a diode config and I will be unplacing diode and the resistor when using MOSFET. for bot of the case the y caps are connected to source and anode of the mosfet and diode respectively. I attached the picture for your reference. Could you please check it and let me know if the polarities and the configuration is right? Thanks alot

The positon of the Y cap looks correct, though you will need to ground the SR pin if you are expecting to use just the diode. I never understood why you would want to use a diode instead of the SR fet, as it sacrifices efficiency. Expense? The SR fet will definitely be more efficient than a Schottky rectifier. However, you have the Y cap grounded on the correct side of both the rectifier and the SR fet, whichever one you end up using.

hi,

thanks for the honest opinion. Yes, mainly its because of the expense. I want to check the difference between both of them but im leaning towards using mosfet because of the losses.

However, I have a question regarding the y caps being conected to the anode side. Does it if i connect the y cap at the point after the elco output filter capacitor?
Also, I hope the Mosfet connection is correct, becasue it is quite confusing looking at the datasheet.
 

That's not really a good idea, as you then introduce the voltage drop of the trace between the output elcap and the rectifier/sync FET, which can act as a noise source to shoot interference back through the Y cap to the primary side. Remember, it's a flyback supply, so the current waveform in the return trace between the elcap and rectifier is all nasty edges with high di/dt. The Y cap connection needs to be right at the rectifier anode/mosfet source. Your mosfet connection is OK as far as it goes, but you will want to lose the short between the SR pin and ground if you want to use the mosfet as a synchronous rectifier.

thanks alot for the input.  Sure, I put a 0ohm res as a place holder.
 

Hi,
Subject-  Transformer winding

Apologies for asking different question, but I hope you don’t mind me asking in this thread.

Regarding the transformer winding , as shown in the attached picture — the manufacturer initially proposed that the “Primary Bias” and “Bias Shield” windings should each use 4P × 0.2 mm wires with 7 turns, effectively creating one combined layer with 8P × 0.2 mm conductors.

However, from a manufacturing feasibility standpoint, winding 8P × 0.2 mm in a single layer is quite difficult. Therefore, they suggested an alternative approach:

• First, wind the “Primary Bias” layer using a spaced winding (“in Space”)
• Then, wind the “Bias Shield” as a second layer using a tightly wound (“in Close”) method

Additionally, they recommended increasing the number of turns for the “Bias Shield” from 7 to 18, so that it fills a full layer.

Do you see any issue with this revised approach from a performance or EMI standpoint? Please let me know

An ETD core seems a strange choice for this application, as the core area is pretty skimpy compared to the overall space  taken up by the transformer. A PQ core might be a better choice, as they have a larger center leg area, resulting in fewer turns, and as a consequence, less leakage inductance. A vertical transformer wrapped with tape and with closely spaced triple insulated flying leads might be a better choice, from an EMI and an ESD immunity perspective. 

Yes, I will switch to PQ for the next prototype.

I have another question regarding the Y caps. The othe side is connect to the anode of the diode/Mosfet source. Where the other side it connected to ? does it connect to dc+ or dc-? please confirm. Normally in other flybacks, it is connected to return path of the primary and secondary.

The other side of the Y cap should be connected to DC+ for better surge immunity. Putting the Y cap to the primary return will degrade the EMI immunity due to ground shifts caused by commom mode surge affecting the InnoSwitch controller.

Hi,

Subject - PCB layout issue

I have a question regarding the PCB layout, and I hope it’s okay to ask it here instead of creating a new thread.

We are facing a situation where there is a relatively large loop between the drain pin of the InnoSwitch-3-EP (INN3679C) and the transformer’s switch node. Since the transformer’s switch node is located at the center pin, it’s not possible to minimize this loop effectively with the current placement.

To address this, we are considering a double-sided component placement, where the IC would be placed on the bottom side directly underneath the transformer. This approach is also recommended in the datasheet.

However, our transformer is THT-mounted, and we would like to confirm whether placing the IC directly underneath it could cause any mechanical/thermal issues or any other issues? 
When it’s acceptable to place the IC on the bottom side, what factors should we consider?
Can the components connected to the IC be placed close to the transformer pins?
Are there any creepage or clearance requirements that we need to maintain in this case?

Could you please advise if this approach is acceptable? This is an urgent topic, as we need to finalize the design for manufacturing.

Thanks a lot for your support.