TNY Auto-Restart

"if the ENABLE/UNDERVOLTAGE pin is not pulled low for 64 ms, the power MOSFET switching is disabled for 2.5 seconds."

This implies that if regulation is not reached before 64ms (i.e all cycles are switching), more power is being delivered to the load and to avoid this, switching is disabled. Basically its a way of saying that a fault condition was detected at the load and switching was disabled to prevent device failure. Overloading/short-circuiting the output causes the device to enter autorestart.

"With a short circuit on my output, I am observing active periods of as much as 200m msec."

Under this condition, find out the switching time(tsw) for 1 cycle. Then, calculate the following:

(64ms*tsw/7.575us). If this number is 200ms, then this behavior is normal.  

I looked at this again, in light of what you said, and discovered the following.

If I connect a load just a little above what the circuit can deliver, I get an active pulse for each clock cycle, and the active period for each restart is approximately 64 msec, as specified in the data sheet.

If I connect a constant current load of about twice what the circuit can deliver, the TNY chip outputs groups of 4 active pules, followed by two clocks cycles without an active pulse, and repeats this pattern.  Therefore, the average frequency of active pulses is 1.5 times the oscillator frequency.  In such a case, the active period for each restart is close to 100 msec, which is approximately 1.5 times the specified 64 msec.

If I increase the load further (e.g.: to short circuit), the active pulses are less frequent (I can't discern a specific pattern, or average frequency).  As noted, the active period for each restart is then approximately 200 msec.

Note that in each case, I tried shorting out the input to my feedback opto, and that made no difference.  So, the fact that it is skipping cycles, is not due to it getting a valid feedback signal.

This leaves me with two questions:

1) It appears that the 64 msec timing is based on a specific number of active cycles, as opposed to a specific number of cycles of the internal oscillator.  Is this correct?  The Block diagarm in the Data Sheet (figure 3) would seem to indicate otherwise.

2) Since there is no active feedback signal, what causes the chip to skip cycles, as a function of the size of the load?

I did some additional tests.

With the output heavily loaded and 85 VAC input, there is a repeating pattern of cycles as follows: 3 active, 2 skipped, 1 active, 2 skipped.  So 4 out of every 8 cycles is active.  As expected based on explanation above, the active time for each restart is approximately 2 times the specified 64 msec.

With the output heavily loaded and 300 VAC input, every third cycle is active.  As expected, the active time for each restart is approximately 3 times the specified 64 msec.

So, this further confirms the observations above, and the two questions in my earlier post remain.

I also now have a third question;

3) Why is the active period for each restart longer for higher input voltage?  (This is true for TNY-3, as well.)

Note that I cut the trace going to the EN/UV pin to be sure no noise was being picked up by the feedback trace - it made no difference.

I also checked the voltage on the high-voltage input capacitor, and the voltage on the BP/M pin.  These are both fine.

Can you attach the observed waveforms please? Drain Voltage, EN/UV pin voltage...etc? 

I ran these tests with a different circuit than I used the first time, but results were similar (if not exactly the same values).  These tests were made with a TNY280, with the EN/UV disconnected.

For each combination of input voltage and load, the attached scope shot of Drain current shows the amount of time the chip is active for each auto-restart cycle.  The corresponding “detail” scope shot shows that for each case where the time is greater than 64 msec, a proportionate percentage of cycles is skipped during the active period.  (For the case where the time is 64 msec., no cycles are skipped.)

Results were as follows:

85 VAC input / 0.92A load:               ~64 msec

85 VAC input / output shorted:          ~64 msec

120 VAC input / 0.92A load:             ~64 msec

120 VAC input / 3.3A load:               ~90 msec

120 VAC input / output shorted:        ~96 msec

300 VAC input / 0.92A load:             ~64 msec

300 VAC input / 2.36A load:            ~105 msec

300 VAC input / output shorted:        ~210 msec

The drain current switching under auto restart is based on an internal 'Auto-Restart Counter'. This count is equal to the number of switching cycles in auto restart and is equal to 64ms/7.575us=8448cycles (Auto-Restart ON Time=64ms;Switching time of one pulse=1/132kHz=7.575us).

The following is mentioned on page.7 of the TNY-4 datasheet:

"Under start-up and overload conditions,

when the conduction time is less than 400 ns, the device

reduces the switching frequency to maintain control of the peak

drain current."

I would recommend measuring the switching time for one pulse (drain current) in auto-restart under the various conditions you have mentioned and multiply that number with 8448. This time should now match the extension in the switching time you see. It seems like the pulses at extremely narrow at higher line voltages, due to which the frequency decreases, thus causing the higher Auto-restart ON-Time.

Hope this helps. 

I'm not sure what you are asking for in terms of measuring the switching time for one pulse.  The time between pulses is always 7.575 usec (+/- 6%), or some multiple of that.
When the chip "reduces the switching frequency," it does not actually change the oscillator frequency, it just skips certain pulses, resulting in a lower "effective frequency."

Getting back to my original questions:

1) The TinySwitch-4 data sheet (pg 4) says that the Auto-Restat ON-Time is 64 msec, without any mention of this being dependent on overloading or skipped cycles.
Additionally, Figure 3 (pg 2) shows that the Auto-Restart Counter is fed by the output of the oscillator - without any information as to whether cycles are active or not.
Additionally, the Parameter Table shows that the 64 msec Auto-Restart ON-Time (tAR) is at fosc (pg 17), which is between 124 and 132 kHz (pg 13).

As I now understand it, the Auto-Restat ON-time is actually 8,448 "active" cycles, which can be much longer than 64 msec. when cycles are skipped.

Is my understanding of the chip's operation correct - and the Data Sheet wrong?  Or, is sometyhing else going on?

2) As to why cycles are being skipped, thank you for pointing out the item about skipping cycles (thus reducing "effective frequency") when conduction time is less than 400 nsec.  I assume that this is the cause of the skipped cycles; however, I am not seeing conduction times less than 400 nsec.  (I am seeing cycles whose conduction time is less than 500 nsec.  Perhaps, even less than 450 nsec.)  Could it be that the 400 nsec timer starts after the Leading Edge Blanking time, or that the Current Limit Delay occurs after the measured conduction time?

As I now understand it, the Auto-Restat ON-time is actually 8,448 "active" cycles, which can be much longer than 64 msec. when cycles are skipped. Is my understanding of the chip's operation correct - and the Data Sheet wrong? Or, is sometyhing else going on?

Your understanding is correct. Autorestart is based on the internal counter. And the datasheet is also correct - on page 4 it does mention that the internalcounter turns on to start counting number of enabled cycles. This counter is reset evertime a switching pulse is inhibited. With regard to the skinny pulses - when the TNYSwitch controller detects this mode it reduces its internal clock frequency to allow for reset of the core. Due to this lower clock frequency the internalcounter takes longer to reach 8448 cycles. Again, everytme a single pulse is disabled the counter is reset

The only reason that 64 ms is mentioned is because most of the time the clock (oscillator) switches at 132 kHz.

Hope that clears things up somewhat.