SR conducts only 25% of flyback cycle with INN3678C

Hi,

Can you please provide the waveform of the Vgs of the SRFET with the FWD pin? If seems there is a false triggering happening in the SR Fet that causes this. What is the value of your series clamp resistor (Rs) in the design and primary clamp diode (Dsn)? 

You may try the following:
1. Increase the value of RS to a certain level. Make sure that Vds will not go beyond the 90% of the IC Vds breakdown voltage. Just a warning, increasing the value of Rs will increase the value of the Vdsoff of the Innoswitch. 
2. Make sure the clamp diode has a standard recovery of below 500nS, these may help eliminating the false triggering.
3. Make sure also that all other components such as transformers and snubbers are properly soldered.

In case that issue persist, please provide us the schematic and transformer constructions (if you have the PIExpert/PIxls documents that would be better).

Regards,
PI-Nanoe

Thank you for your advice!

I increased Rs from 24Ω to 33Ω, which slightly lengthened the pulse on SR. However, this is still far from a full switching cycle. Ds has a recovery time of less than 500ns. I don't think it is the problem.

Attached are two pictures of the waveform at SRFET's drain measured at 40% load condition. "Cycle.png" is a full switching cycle. Yellow is the primary drain with 100V/div (100VDC input) and looks IMHO normal. Green is measured at the drain of the SRFET. It also looks normal, except for the problem that it switches less than half. The picture SR-Drain.png shows this again zoomed in.
What strikes me is that the rising edge on the primary side is relatively soft. The peak before Ds switches through is also relatively small. The curious thing is that I had a second prototype with an identical assembly (unfortunately burned down), which showed very steep edges and a full switching cycle on the SRFET. The transformer is an OTS component (Wuerth 7508116314, see attached data sheet).
Do you have any idea where the soft edge could come from and whether it could be the reason for the short switching time on the SR?

Hi,

Can you please provide the capture waveform of gate-source voltage across the secondary side FET. Base on the waveform you provided, the SRFET is false triggering.  I would like to confirm if this is the issue. If this the case, you may need to optimize the transformer because of winding capacitance.

You may try the following alteration one at a time if this will help, however this may not provide significant change rather than optimizing the transformer.

1. Use lower Rds(on) SRFET.
2. Add parallel schottky diode across the SRFET
3. Add 330pF between SR pin and GND pin
4. Optimize snubber of SRFET and Clamp circuit.

Regards,
PI-Nanoe

I can capture gate waveform tomorrow, but I'm quite sure, that waveform is a near perfect rectangle with right levels. The timing matches exactly to the conduction time of SRFET. My first guess was a defect SRFET but it was full functional. Again Vgs is around 1.1V and Rds on is around 15mΩ.  See attached datasheet.

Yes, I will will give your suggestions a try. And again. My second prototype with same transformer shows much sharper edges. So I will try to exchange the transformer too.

Thank you!

Here is also the waveform of the SRFET gate. As predicted, an almost clean rectangular pulse. The ringing on the primary clamp and the SRFET is so low that I don't think further optimization will have any effect.
What strikes me, however, is that the SR pulse ends after exactly 1.5 µs (in a wide range of the load). The datasheet has a note under Figure 15 that says: “If t1 + t2 = 1.5 µs ± 50 ns, the controller may fail the handshake and
trigger a primary bias winding OVP latch-off/auto-restart.” 
I don't see a latch-off/auto-restart, but the timing would basically fit. Can you tell me what the “Handshake with Body Diode Conduction During Flyback Cycle” actually means?

Hi,

Do you have the capture waveform that contains multiple switches of the Vgs? It seems the Vgs ON time is too short. This short turn on of Vgs normally caused by transformer capacitance, layout and switching components. You can provide us the layout of the design or of your design files for us to review. If you do not want to share publicly the design, you can raise the issue in our customer support at this link. 

Regarding the “Handshake with Body Diode Conduction During Flyback Cycle”, this only means that during start up condition (before handshake), if body diode behaves like in the figure 15, the InnoSwitch will not proceed with the handshaking which cause the InnoSwitch continue to switch until it may go OVP. As much as possible, the drastic change of t1 should be greater than the 1.5uS to have a successful handshake.

Regards,
Nanoe

Thank you, this helps me a little bit further.
Yes, I captures multiple cycles too, but with constantly too short pulses. Meanwhile I had changed near every componen, except the transformer and the Innoswitch, without any significant effect to the waveform. So I decided today to rebuild the cuircuit with 3 new prototypes. I want to test different transformers and different pcb-layouts. Maybe my current layout was not the best. ;)
I need a rock-solid design for production...