HiperLCS control loop instability
Hello,
I have been working on a design based on LCS705HG for a 385Vin, 12Vout, 250W supply. The simplified schematic and PIxls files are attached. The completed circuit powers up and the waveforms look good, but I can only get about 25% power out before the switching frequency begins to jitter, causing wild swings in the HB current waveform and ripple on the output. The current waveform looks similar to those posted by user [telcobridges] in this thread: https://www.power.com/forum/high-power-design/2015/lcs708-stability-problem/ . I believe I have traced the problem to insufficient phase/gain margin as proven by a frequency response analyzer. However, PIxls does not sufficiently specify the control loop compensation components, and AN55 is similarly unhelpful, so I am unsure where to go from here. Is there another appnote available on control loop compensation for this supply architecture, or is there anything obviously incorrect with the compensation scheme shown in the attached documents?
Thank you!
Comments
I am sorry if I missed something, I can not find your schematic and PIXL. could you repost it this time?
There are some suggestion from the link you found on the silimar issue, do not know if it works for you. we can start with your schematic and PIXL design.
The documents were attached to the original post, but hidden. Support personnel must not be able to see attached files for which "Display" is unchecked? In any case I've un-hidden them.
From your schematic there are a few components related to the loop performance. the first thing we suggest you to check is below:
Your C34, C12, and R30. R30 sounds too big. start from 1k and try increase the resistor and see if that impact your loop. Refer to LCS design examples on website as a starting point. for example, 10nF&1K only.
beyound this, C25&R23; and R36 and C33 will have some impact on loop gain.
I have redesigned the loop compensation somewhat, and now have mostly satisfactory results (see attached updated schematic), but my phase and gain margins are too small for a production design. I need a 10-20dB gain reduction across the board, but it seems I've decreased the gain as much as PIxls allows. I tried reducing R34 and the gain remained unchanged in the area of interest (3-30kHz). I would try increasing R29 but it already appears to be near the optimal value as per the recommendations in AN55. What would be a good change to make in order to provide gain reduction without violating the TL431 minimum regulation current?
Thank you!
| Attachment | Size |
|---|---|
| LLC-2.pdf (103.5 KB) | 103.5 KB |
did you try to fine tune the R33?C37 in parallel with R34?
Can someone from PI please comment on this? I understand priorities and delays and all that, but ten days is an unacceptable turnaround time for a support query.