10W SMPS Failures
Hello,
We have designed a 5V, 10W SMPS.
We manufacture approx 5000 SMPS per year since last 5 years. We found that there are almost 50nos per year are getting damaged.
We worked on component selection (manufacturer). But still the issues are not resolved.
It is found that in most of the cases, TOP244, bridge rectifire and in some cases transformer is getting dameged.
Efficiency is found out to be 60%. So is this the area of concern for the failures ?
Is transformer failure pointing to saturation current from TOP IC ?
Attaching the schematic.
Hoping for the quick reply.
Regards
Comments
Thank you very much for your reply.
Regarding the other components failure such as input capacitor, bridge rectifier, we do not find any exact cause.
We have worked on the component(manfg) selection. Also there are some protection circuit at the mains input.
The efficiency of the smps is found out to be less than 60%. So is this low value resulting in the degradation of the components over the period ?
Attaching the transformer design detail file.
Regards
Hi,
I agree that the efficiency less than 60% is not reasonable, maybe this is the first thing to check. Before going forward, what s the condition of the efficiency measuement? What is the input votlage and load condition? What is the method of the measurement? You may refer to following link from PI to setup the efficiency measurement correctly:
http://www.powerint.com/en/pi-university/courses/techniques-measuring-drain-voltage-and-current
Hi,
To measure the efficiency, I have a variable AC voltage source with RMS voltage and current indicator on it.
So the input power to the SMPS in calculated from those readings.
Output is 5V, 2A.
I agree the method you suggested to find the input voltage and current is more accurate, but i am unable to get that much resources at this time.
Looking at the failure components, this much energy loss seems to be in primery side.
Any pointer ?
Regards
If the efficiency measurement method is not properly setup, then it is not reasonable to clarify the efficiency data is not reasonable.
Yes, it looks like some high voltage occurs from the primary side which cause the failure of the bus voltage, bridge...ect, do you have any clue that the failure is related to the surge voltage from the input, what is the surge level of the power supply you designed? Did you put any MOV in the input of the power supply?
Hello,
Yes we have MOV in the design (shown in schematic attached) rated 320V.
Over voltages must be trapped by this MOV. MOVs are not at all getting damaged in the failure cases.
TOP IC also have over voltage protections. Transformers are tested for 2-3KV.
Can there be a design related issue ? Are the current sense and line sense resistor properly selected ?
In most of the failures, TOP Switch is damaged.
Resistor R4, R12, R15 are meant for currenty limiting. So incorrect values may cause transformer core saturation at startups and output transient conditions along with increased power dissipation in TOP switch.
Any pointer ?
Hi,
Waiting for your kind reply.
Hi,
Did you use the PI-expert software to help to design the power supply? What is the flux density of the transformer core you used to design the transformer, this information can help to know how much margin of the design from getting transformer satuated. Topswitch actually integrates a SOA protection mechanism, that prevents the MOSFET from broken enven with transformer saturation at some worst condition.
If you think transformer saturation could be the potentional reason, one interesting test you may consider to do: Short the secondary diode to the output return, heat the transformer to be 100C, then power up the power supply with highest input voltage that it designed for. Please record the drain current wave forms, and set up the scope properly to get the highest drain current waveform during the start up. Check if the drain current start to take off rapidly with di/dt higher than the Vbus/Lp. Then you can find out if the transformer is marginable designed or not.
Hope this is helpful.
Hi,
We are carring out the test you mentioned.
Till then, can you suggest us the formula for calculating external current limit and UV/OV resistors for this design ?
Hi, Please refer to figure 54 in the data sheet for external current limit:
Data sheet link: http://www.powerint.com/sites/default/files/product-docs/top242.250.pdf
For the UV/OV calculation, please refer to Vuv=Iuv*Rls, Vov=Iov*Rls; Rls is the resistor value in L pin, and Iov and Iuv is from the parameter table in the data sheet.
Hope this is helpful for you.
Hello,
We carried out the test you mentioned.
Efficiency test: As per the setup mentioned in the
http://www.powerint.com/en/pi-university/courses/techniques-measuring-drain-voltage-and-current
we found out the efficiency to be 63%.
Transformer design verify test: As per the setup you mentioned, it was found that transformer design is not at all marginabally designed.
So the problem is still open. Why there are so many failures in TOP switch IC and other primery side components?
Regards
The efficiency is low if you are sure the set up of the test is correct.
So from what you mentioned, the transformer is well design which it does not go to satuation with high temperature. Do you have any clue of this failure related to the ambient evironment, like it mostly failed in the application area like hot temperature, or high huminity? You may consider to contact us to request RMA, as it seems to me the reason is not obvious.
Yes the set up to measure efficiency is absolutly as mentioned in the datasheet.
What can be the reason for this low efficiency then ?
Can we improve it?
I do not uderstand what 'RMA' is, what is it for?
Regards
Hi,
If the efficiency is 60%, it can be for sure improved. Please make sure you follow this instruction to do the efficiency measurement:
http://www.powerint.com/en/pi-university/courses/techniques-measuring-efficiency
Did you use the input power analyer to measure the input power? The RMA is Return Merchandise Authorization.
Yes we already used both the methodes to measure the efficiency.
With 4 DMM approach efficiency comes to be 62% and Watt meter it comes to be 63%.
So what are the the measures we sould work for to improve the efficiency?
Yes we already used both the methodes to measure the efficiency.
With 4 DMM approach efficiency comes to be 62% and Watt meter it comes to be 63%.
So what are the measures we should work for, to improve the efficiency?
Hi,
What is the tes condition when getting 60% efficiency, is it 90Vac input and full load?
There are many ways to improve the efficiency, here are some hints:
1. Use fuse + NTC instead of fusible resistor in the input, this can decrease the loss on the fusible resistor.
2. Design the transformer with lower leakage, like sanwich structure.
3. Optimize the transformer design to decrease the cooper and core loss. What is the working mode when you designed the transformer, CCM (Continuous Current Mode) or DCM(Discontinuous Current Mode)? Did you use the PI-Expert software to help you design? If yes, would you please attach the file, that I can further support you.
4. Use schottky diode on the output side.
Hope this is helpful
Hi,
I did have a check of the schematic, I did not see anything obivious wrong.
It is hard to conclude the failure is caused by the satuation current to the Top Switcher. Moreover, there is SOA protection integrated in TopSwitcher which protected the device from damage during the fault condition with very high drain current. Do you some some components else damaged during the failure? You said the transformer and bridge got damaged in some cases, have you figured out what are the root causes of this failure? If you have the PI-spreadsheet design, I can have a check of your transformer design if you like to.