Hiper Minimum Load

Pls. take data and plot the following:

Bulk cap voltage vs. load current

and

LLC operating frequency vs. load current

Start at full load and work your way to lower and lower load current, until the output voltage rises to about 25~26V.

First, double check that the bulk cap voltage stays in regulation. It should remain within regulation. If it rises and stays high, there is something wrong with your PFC feedback loop. However, I do not expect this to be the cause of your problem.

Next, tell me the frequency at full load, half load, and at 10% load.

Also pls. post your primary current waveform at full load, half load, and 10% load.

What is the transformer leakage inductance as measured on the primary with one phase of the secondary shorted? With the other phase of the secondary shorted (other phase is open)?

What is your resonant capacitor value?

Next, examine the LLC frequency right at the point where reducing load further causes an increase in output voltage. Look for the point at which the frequency suddenly stops rising as you reduce the load. Note if the frequency rises smoothly then stops, or if it begins to rise rapidly just before it stops. Frequency is supposed to rise as load is reduced so as to maintain output regulation.

If the frequency begins to increase rapidly as you decrease load just before it stops increasing at the loss of regulation point, it may be that your LLC resonant tank needs to be redesigned - your operating frequency at nominal conditions is too far above resonance. This means the frequency needs to rise a lot as you reduce load. The primary current waveform shape at half and full load will tell me if this is true. If so you need to add primary turns so that nominal operation is closer to resonance; this will bring operating frequency closer to resonance. You will need to reduce the primary resonant capacitance in order to maintain your desired nominal operating frequency.

If LLC frequency rises smoothly before it stops, then it may be that the max current from the optocoupler going into the FBL pin is not enough. Remember that frequency rises as the current entering the FBL pin increases. The maximum frequency the opto can push into the FBL pin is not enough.

Next, check the voltage across the opto transistor at the minimum load point where the output begins to climb. If this voltage is ~0.3 V, then the opto is saturated and the resistor between the opto and the FBL pin is too large. Reducing this resistor will increase the max current from the opto and increase the max frequency. If the voltage is >0.5V then the opto isn't saturating and either the opto gain is too low (use a 'C', or 'D' suffix opto instead of 'A' or 'B'), or the opto LED isn't getting enough current, and the current limit resistor in series with the opto LED needs to be reduced.

If I optimize per your instructions will I be able to operate with no load?

Yes

This is actually a 190 V design.
Bulk cap voltage vs. load current

385 V at all currents

Next, tell me the frequency at full load, half load, and at 10% load.
1.08 ADC @ 192.8 VDC 1.77 AAC @100 KHZ 90% load
0.73 ADC @ 193.3 VDC 1.49 AAC @102 KHZ 60% load
0.14 ADC @ 194.3 VDC 1.01 AAC @108 KHZ 12% load
0.08 ADC @ 196.7 VDC .46 AAC @189 KHZ 7% load
0 ADC @ 240 VDC .46 AAC @250 KHZ No load

Also pls. post your primary current waveform at full load, half load, and 10% load.

What is the transformer leakage inductance as measured on the primary with one phase of the secondary shorted?
70 uH is what it is marked, I am getting a tester to do the check.
With the other phase of the secondary shorted (other phase is open)?

What is your resonant capacitor value?
33 nf.

Next, check the voltage across the opto transistor at the minimum load point where the output begins to climb. If this voltage is ~0.3 V, then the opto is saturated and the resistor between the opto and the FBL pin is too large. Reducing this resistor will increase the max current from the opto and increase the max frequency. If the voltage is >0.5V then the opto isn't saturating and either the opto gain is too low (use a 'C', or 'D' suffix opto instead of 'A' or 'B'), or the opto LED isn't getting enough current, and the current limit resistor in series with the opto LED needs to be reduced.
The voltage at minimum load is .4 V.

Your first problem is that the PFC output voltage is climbing very high at 0 load. You are getting 240V, when the nominal setpoint is ~190V. Fix this problem and your LLC regulation problem will most likely go away.

190 V is not the PFC Voltage it is the output voltage. THe PFC B+ is always 385 V.

In that case:


The root of the problem is that the maximum frequency the feedback loop can apply to the HiperPLC, which is 250 kHz, is not enough to regulate at 0 load. I can see this because the voltage across the opto transistor is 0.4V.


There are several things to try.


1) Add 1-2 turns to your primary. This will make your LLC operate below resonance, which makes it easier to regulate at 0 load (reduces frequency to regulate at 0 load). You may wish to decrease the resonant capacitor value in order to get nominal operating frequency back up to 100 kHz.


2) Increase the current the opto can force into the FB pin. (decrease the value of the resistor between the opto emitter and the FB pin) This will increase the maximum frequency. If you increase this current beyond the current that the FMAX resistor is pushing into the FMAX pin, the LLC will go into burst mode, and this will definitely allow 0 load regulation. However, this may cause undesirable audible noise.