Output Disable Setup Time

Pls. clarify what you mean by "output disable setup time".

A mean parameter in TNY253-255, TNY256 and TNY263-268 data sheets (there's parameter, but there's not any description).

I have only one explanation posted at this forum by PI-expert:

"TinySwitch I&II samples the enable pin at the internal clock rate. For the output to be enabled or disabled for a corresponding clock, the enable pin signal must be present for the required setup time. If the condition is not met, then the output state will be delayed by one clock cycle."

But I guess it is not quite conform to description of ENABLE pin operating (according to data sheet).

The basic operation of the Tinyswitch is as follows:
At every clock cycle, it "decides" whether or not to turn on the output MOSFET for that cycle. The decision depends on the state of the Enable pin at that clock edge. This pin has a setup time spec, tDST. This spec however, is not very relevant for the design of the PSU.

Does this answer your question?

I agree with your description of basic operation, I completely agree this spec is not very relevant for the design of the PSU.

But I just can't understand how this parameter can be specified without any condition or mode. I suppose setup time as a rule depends on input signal.

I question the wisdom of this spec.

Thanks for your reply, thanks for reading my post.

Hi,

Is there a problem you are trying to solve?

Regards,
PI-Tucker

Actually there is only disturbing curiosity after reading several data sheet.

hi

Thank you

wilson

[url=http://www.laptop-computers.co.za]Laptop Fanatic[/url]