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DER-507 EMI fails

Posted by: Michele Mocellin on Wed, 10/13/2021

I'm working on non-isolated switcher based on DER-507 design, the output voltage is correct ( 5V ) and in my application the output current is approximately 20mA.

So I did the EMI test, I tested my custom board in no-load condition and in normal use condition but it failed in any case, the only different with DER-507 desing are component layout and free wheeling diode D2 that has a recovery time >75ns. 

I know it's difficult to have a fully correct answer, but do you think the wrong recocery time of free wheeling diode may cause EMI test fault ? Or do you think is only a layout problem ?

I am attaching the test charts.

Thank you

Files

Attachment 大小
LOAD CONDITION_0.JPG 107.13 KB
NO LOAD CONDITION_0.JPG 105.04 KB

评论

Submitted by PI-Salt on Thu, 10/14/2021

Hi Michele Mocellin,

Thank you for showing interest in Power Integrations and its product

Would it be possible for you to provide the PCB layout design and the PIXLS spreadsheet you used for the design? 

Component layout has a big effect on EMI so it would be beneficial if we could see the PCB layout. Additionally, can you also provide the output ripple waveform?

 

Thank you.

Submitted by Michele Mocellin on Thu, 10/14/2021

Hi,

Thank you for your quickley replay.

In the attachments you can find gerber files and BOM, please consider that PCB desing is not my primary business, so the primiry function of this desing is to have functiona prototype.

For the output wave form can I use a normal oscilloscope probe or do I have to modify it like your datasheet suggests ?

Thanks

 

Attachment 大小
GERBER.zip 47.22 KB
SPREAD SHEET.pdf 66.92 KB
Submitted by PI-Salt on Thu, 10/14/2021

Hi,

Upon reviewing the layout from the gerber files, there are some layout changes needed. It is highly recommended to minimize switching loops and minimize overlapping traces on the power section which can be the source of EMI noise. To aid your re-spin of the PCB layout, it is recommended to copy the existing DER-507 layout since it already incorporated best practices when it comes to layout. Plus, you can verify your EMI results on DER-507 test data so you can see if there are difference from your board vs DER-507 board. Also note the load use from the report. I think there is no no-load condition test for the EMI given in the report because it is not usually not tested. 

Furthermore, it seems that there are two separate circuit integrated in the layout, I would suggest first to isolate the first stage, which is the DER-507 and test it first if it passes the EMI. Then, incorporate the second stage and test the EMI again. Having long recovery time for the freewheeling diode affects the Ids,spike in your circuit and in turns results to high dv/dt on the drain node which can be also a source of EMI noise. 

Please consider the layout in your design because it highly affects almost everything, especially the EMI.

I hope this helps. Thank you.

Submitted by Michele Mocellin on Fri, 10/15/2021

Hi,

thank you for yor explanations !

About two separate design, during EMI testing section after first bad result I isolated the DER-507 stage to testing it alone, with and without load (200 Ohm resistor), but as I said it does not pass the test, so we individuate the noise on switcher circuit.

Anyway in the attachment there is the wave form output with a load of (200 Ohm resistor).

Submitted by PI-Salt on Fri, 10/15/2021

Hi, 

The DER-507 board EMI was evaluated at 142 Ω resistor load (5V/0.035A as per specifications) - you could try to test this using this resistor load since it is design at this loading condition. If it still fails, you might want to consider to relayout your PCB board since it has a big effect on EMI.

If you have further questions, please let us know. Thank you.