2026-04-09T18:54:39 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstchip.dat"
2026-04-09T18:54:39 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstxnet.dat"
2026-04-09T18:54:39 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstxprt.dat"
2026-04-09T18:54:39 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstdmlmodels.dat"
2026-04-10T10:29:57 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstchip.dat"
2026-04-10T10:29:57 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstxnet.dat"
2026-04-10T10:29:57 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstxprt.dat"
2026-04-10T10:29:57 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstdmlmodels.dat"
2026-04-20T09:50:58 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstchip.dat"
2026-04-20T09:50:58 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstxnet.dat"
2026-04-20T09:50:58 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstxprt.dat"
2026-04-20T09:50:58 ===> "F:/APPS_FILES/PUBLIC/DESIGN EXAMPLE REPORTS/DER-1019 TOP7 4 - 165-265 VOUT 89V 4A/SCHEMATIC_PCB/REV G/allegro/pstdmlmodels.dat"
