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Why does Power Integrations use primary clamps in offline flyback designs?

Posted by: treez on

Hi,
As you know, Power integrations kindly offers DER reports for offline flybacks up to and above 100W. All Power integrations example designs (above 10w) include RCD clamps across the flyback primary.
However, Fairchildsemi.com offer an offline flyback controller called FSCQ1565. As seen in its datasheet and application note, this controller needs no primary clamp whatsoever….all it needs is an ~1nF capacitor to be connected from drain to source of the power FET….even for flybacks up to 100W and more. The internal FET in FSCQ1565 is only 650V rated.
(this is seen in AN-4146 page 19, where you can see a 100W Offline Flyback SMPS with no primary clamp whatsoever)
You have to say, one of you has got it wrong (Power integrations or Fairchildsemi). Who has got it wrong? And Why?

FSQG1565 datasheet
https://www.onsemi.com/pub/Collateral/FSCQ1565RT-D.pdf

AN-4146 (FSCQ1565)
https://www.onsemi.com/pub/Collateral/AN-4146.pdf.pdf

Comments

Submitted by PI-Chloe on 01/27/2021

Hi treez

Adding a capacitor across in FET drain-source is not a practice because it add to the total switching losses of the FET. For an external FET power supply, FET selection should have the lowest drain to source capacitance.
At turn-off, the capacitance across the Drain-Source is charge to a high voltage. Once the FET turns on the energy across the capacitor is discharge to the FET.

Fairchild Semi’s FSCQ1565 is a Quasi Resonant (QR) converter. FET will turn-on during the minimum Vds. This will lessen the effects of the turn-off switching losses since the energy in the capacitor is lower due to low Vds at the point of turning-on. But still there is still switching loss added to the energy stored by the external capacitor. FSCQ1565 allows this due to its QR function. FET will become hotter since it will be a discharge path of the external capacitor energy.

Now, it is not just Power Integration design have this. You can check other IC (FET+Controller). They uses RCD clamp rather than using capacitor in parallel to the Mosfet. It is not prefer to use capacitor in the FET drain to source as snubber due to increases losses in the FET.

Thanks

PI-Chloe

Submitted by treez on 01/27/2021

Thanks, in truth, the FSCQ1565 flybacks amaze me. I have never seen a flyback without an RCD clamp (or a D/TVS clamp), let alone a 100W offline flyback without an RCD clamp. I think you were very kind to the FSCQ1565. Surely what they are doing is utterly outrageous?.....you simply cannot safely do a 100W offline flyback by having no RCD clamp and just a 1nF cap connected Drain to source?
When i do contract work, customers show me the FSCQ1565 datasheet/App note, and ask me why i have to use an RCD calmp when the FSCQ1565 does not have it.

Submitted by PI-Chloe on 01/28/2021

Hi Treez, ,

The FSQ1565 permit this because of the QR function.

But then again, this is not a popular approach since this will add losses in the FET.
Energy capacitor will be dump to the FET during turn-on.
Increasing losses and increasing thermals of the FET.

The RCD clamp will take away the increase FET power losses and thermals for a more reliable power supply.

Thanks

Regards

PI-CHLOE

Submitted by treez on 01/28/2021

The thing is, if leakage inductance is 15uH or more, then the drain voltage will go above 650V if the [v(in)+v(reflected)] voltage is 421v or more, and the peak primary current is 4.1A or more. This means the FET will be overvoltaged.
This isnt too mention the situation of output overload occurring at max vin......even though overload protection will eventually kick in, the drain will be overvoltage at first.
Also, with no primary clamp, the current in the secondary diode rings at high frequency throughout the secondary diode conduction period.
Also, what do you think would happen if you run the SMPS at max load, then you wind the VAC input slowly down to zero VAC input (FSCQ1565 has no UVLO)......surely the drain would get overvoltaged?, specially since people tend to use the FSCQ1565 version which has a very high peak primary current threshold of 8 Amps.

Submitted by PI-Chloe on 02/08/2021

The snubber that the FSCQ employs is the capacitor in parallel to the Mosfet. It slows down the voltage at turn-off. Again this has an impact on efficiency and thermals of the FET. Designer should size up the transformer and snubber based on the allowable Vspike. Design of low Leakage inductance transformer. Proper sizing of the snubber circuit (RCD or Capacitor in parallel to the FET).
Yes if there are no primary clamp or snubber, the voltage on the FET can be above the FET rated voltage.

When the SMPS is running at max load and you decrease the Vac input to 0Vac. There will be no occurrence of drain overvoltage. Drain Voltage will be Vin + Vreflected. And Vin is very low during Vac decreases to 0V.
Vin assuming this is below 100V when you decrease input voltage.
Vreflected is dependent to the turns ratio and output voltage
Vspike is controlled by the snubber (RCD clamp or via capacitor in parallel to the FET)