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INN3670C frequency not stable -> noise

Posted by: machfax on Fri, 07/09/2021

Hi

I am using a INN3760C for a 24VDC 100W power supply. I had a lot of emmissions over the air because the INN3670C was switching into the continuous conduction mode and back between 1-3A load. from 3A to 4A it was ok.

Then I placed 100Ohms and 2nF in parallel with the RFB Upper. Now this continous conducted mode switch is solved, but the switching frequency is not stable and this is produciong a lot of noise. Any idea to improve this schematic?

The plots are showing the primary voltage over D-S and the current and the secondary volate over the FET Q1.

Files

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plot 38.12 KB
switcher original 185.49 KB
RC improvement Feedback 82.85 KB

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Submitted by PI- MarcusJoaquin on Tue, 07/13/2021

Hi Machfax,

Can you please send the schematic and PIExpert spreadsheet that you used.

Then your last statement"The plots are showing the primary voltage over D-S and the current and the secondary voltage over the FET Q1", are you trying to show us the waveforms?

No attached waveforms, can you try to send the waveforms also.

 

Thanks!

Submitted by machfax on Wed, 07/14/2021

I added the files, but they are not visible, trying again

 

첨부 파일 파일 크기
plots 255.26 KB
design 993.5 KB
Submitted by PI- MarcusJoaquin on Thu, 07/15/2021

Hi Machfax,

The problem you encountered is maybe related to pulse bunching and one of the cause is due to layout issue at the secondary.

Here are few things we can do before we review the layout:

1. Change the voltage divider resistors R4 (Rfb_upper) to 180k-ohm from 1.7M-ohm and R6 (Rfb_lower) to 10k-ohm from 95.6k-ohm.

2. For the RC feedforward network or the RC across R4, instead of 100-ohm and 2.2nF change it to 10k-ohm and 10nF.

3. Make sure the feedback resistors R4 (Rfb_upper) and especially R6 (Rfb_lower) and C13 (330pF) are close to the FB pin of the IC. With C13 as the closest one one to the FB pin to make sure filtering is useful. The grounding must be coser with pin2 or the GND pin.

Thanks!

Submitted by machfax on Thu, 07/15/2021

I changed the filter stage to 604k upper and 33.2k lower, parallel to the upper I use a 220k 1nF. Now the continuous conduction mode is ok, but the frequency has still some "gaps" with higher frequency spaces which causes the noise. The EMC is ok, but the noise is still there.

첨부 파일 파일 크기
filter stage 10.42 KB
Submitted by PI- MarcusJoaquin on Fri, 07/16/2021

Hi Machfax,

Is the noise you are referring to is the output voltage ripple noise?

Have you tried the voltage divider values for the feedback and the RC feedforward values across the Rfb_upper?

Can you send us your PCB layout? I can open altium and cadence, if your PCB layout software apps is different from this two I mentioned maybe send me a PDF copy of the layout.

Thanks!

 

Submitted by machfax on Fri, 07/16/2021

the noise is there if the frequency has this change according to the picture. This is happening during 1-3A, below 1A its ok and over 3A its ok aswell.

 

첨부 파일 파일 크기
frequencydiff.jpg 146 KB
Layout 5.83 MB
Submitted by PI- MarcusJoaquin on Fri, 07/16/2021

Thanks Machfax, I will review the layout.

Then I needed some other information while I'm reviewing the layout.

Based on this frequency, does it create audible noise? The reason I am asking is what are the impact of this frequency changes in your design.

Ripple Noise, Audible Noise, EMI? I would like to know in what functionality or performance does your power suppy affected.

For audible noise, I suggest to make your transformer varnish and place epoxy at the gap and corners of the transformer core.

 

Did you try the Rfb_Upper, Rfb_Lower and the feedforward RC values across the Rfb_Upper I am suggesting?

 

 

 

HI Machfax,

Aside from my previous receommendation, below are my layout review and suggestions.

1. Add 2.2uF capacitor after the output inductor L2. Put the capacitor across +24_Vout and GND. 

2. Put a capacitor across Rsense (R20 and R21), value of capacitor is from 10nF to 100nF, this will reduce pulse grouping.

2. Transfer R6 on top of C13 or we call it piggy back R6 on C13, although you are using a ground plane the traces of R6 ground connection seems far at the IC GND pin (PIN 2).

3. The bypass capacitor C16, transfer the GND_SEC connection to the pin 2 of the IC. 

4. Put a ceramic capacitor up to10uF across VOUT pin (Pin 6) and GND pin (Pin 2). This would reduce output ripple.

5. Ground traces for IC GND pin, COUT (C11/C12) and feedback components have to be star connected at a single point of RIS (R20/R21).

 

Submitted by machfax on 일, 07/18/2021

Hi MarcusJoaquin

Thanks a lot for your inputs. I already added a 10uF to the output between VOUT and GND. The other inputs I will implement and try out.

It makes audible noise in a frequency about 10kHz.

Thanks a lot and I will out your inputs.

Regards, Dominik