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Gapping the Transformer in Two Transistor Forward converter (DER-472)....why the gap?

Posted by: treez on Mon, 12/21/2020

This concerns gapping a Transformer for a Two Transistor Forward SMPS. -And why a gap is needed!

Page 21 of DER-472 shows that a gap is needed in a 300W Two Transistor Forward. The second picture down (pg21) shows a gap being made with 0.02mm tape. The reason for the gap is given at the bottom of page 31. It says that the gap must be present so that the “no_load resonant frequency Between L_PRI and C_PRI does not get too low”. -Presumably , there is a problem if this resonant frequency becomes the same as the switching frequency (??)


Does anybody know why the primary resonant frequency, as discussed above, is so important, such that a gap is needed?

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Submitted by PI-Wrench on Mon, 12/28/2020

Gapping is generally only an issue with a TFS-2 design operating at 132 kHz rather than 66kHz. At the higher frequency, a large magnetizing inductance may not allow the primary waveform to ring down far enough to charge the supply for the topside fet, which can result in skipped pulses at light load. You can add an extra aux winding to feed the topside fet, but that's extra cost and complexity. Gapping the transformer reduces the magnetizing inductance sufficiently for adequate ring -down to keep the topside fet running properly at light load.

It doesn't require much of a gap. For a vey small gap, grinding is insufficiently precise, so a shim gap is used. Polyester film would work, but it's hard to keep the shims in place while the cores are being fitted, hence the use of polyester electrical tape with a 1/2 mil (0.013 mm) substrate thickness. Trying to glue the shims in place would likely result in a gap that is not only larger than desired, but inconsistent as well, in addition to adding another fiddly manual step to the transformer construction.

All this is generally not an issue with a 66 kHz design.

Submitted by treez on Sat, 04/24/2021

Thanks, but why does it matter that  there will be skipped pulses in light load?

It surely wont affect regulation that much?

Submitted by treez on Sun, 04/25/2021

Hi, I dont see why the top side fet has to run properly in light load. As long as it gets a few power pulses now and again then the converters output caps stay charged up.

Is the gap not to prevent saturation due to this idea of having a larger primary reset voltage  higher than vin, which causes saturation  in those few occasions when the topside capacitor hasnt quite charged up enough yet?


This idea of having the higher reset voltage allows the higher duty cycle than 0.5, but it surely comes with a downside...that is, until the topside capacitor has charged up, you dont have enough voltage to properly reset the transformer, and so saturation can ensue?

Submitted by PI-Wrench on Mon, 05/03/2021

The problem is, you don't know at what "light load" you will start to have a problem. This is especially a problem for a higher power app with a larger core, with more native ungapped inductance. Gapping solves the problem at the cost of a little higher Imag.