InnoSwitch4-QR. Using a SR FET with gate threshold voltage higher than 4.5V

Hi Alberto,

We currently don't have any implementation like this wherein an external gate driver is used across the SR Pin to control the switching of an SR FET.

There are also major concerns in the timing of SR Pin (when it will pull high and low the signal as its output) when operating in DCM as the SR Pin relies on the signal seen by the FWD Pin with respect to the secondary GND Pin, so adding a high input capacitance system (external Gate Driver) will affect the timing. 

May I inquire what are the reasons why would you want to use a 5V of Vgs(th) for your FET? 

You can also find more specific details on choosing SR FET by checking page 18 of the design guide below:

an-72_innoswitch3_family_design_guide.pdf (power.com)

Thank you.

Hi PI-Book,

May I inquire what are the reasons why would you want to use a 5V of Vgs(th) for your FET?

In my opinion it is quite difficult to find 150V logic-level power FETs from the major manufacturers (Onsemi, Vishay, Diodes, Infineon, Nexperia, STMicro, Diotec, etc...) especially in low-profile SMT packages like DFN3333 or DFN5060. That's why I was asking if there is a way to increase the drive voltage.
Another option is to use GaNs as SSR FETs instead of standard mosfets. I have seen a few interesting parts, but I don't know if there are other implications to take into account. I have started a new thread on the issue here 

You can also find more specific details on choosing SR FET by checking page 18 of the design guide below:

an-72_innoswitch3_family_design_guide.pdf (power.com)

I have some questions about AN-72:

1. In the requirements, you state that Crss should be less than 35pF and Crss/Ciss < 2%.
   1. Crss and Ciss are not fixed values: they vary substantially with VDS. This is an example. Which point of the curve should I take as a reference for evaluating Crss and Ciss?
   2. Do these two requirements need to be verified at the same time? I mean: is it ok if we chose a FET with Crss>35pF, but with Crss/Ciss<2%? or viceversa, is it ok if we chose a FET with Crss/Ciss>2% but with Crss<35pF?
2. Regarding the requirement on the body diode recovery time Trr<40ns. I guess this requirement is important only when the flyback works in CCM, as in this case it is "hard-switched". If we design a flyback that can work only in QR mode, the diode is "soft-switched" and the requirement on Trr is not important.