HiperLCS2 has any downfalls?

Hi,
The HiperLCS-2 controller is an LLC controller which features all the control and primary FETs on a chip...and it has a sister chip which does synchronous rectification for this LLC controller. It does the synchronous rectification in a highly reliable manner using secondary side control and a noise-immune "fluxlink" mechanism to port the fet drive and feedback signals across the isolation barrier.
Having both primary FET drive AND synchronous FET drive originating on the secondary side is THE most reliable way to do synchronous rectifier drive for an offline power supply.

It even purports to be doing "current mode control of the LLC stage".

In short, this chip-set will surely mean the end of most power supply consultancies?....because with this chipset, virtually anybody can do highly efficient offline power supplies with synchronous rectification up to 60V , 12A output.

Indeed, it is the only synchronous rectifier controller on the entire www that shows a demo board with synchronous rectifiers for >50V outputs.
It even has automatic dead time optimisation!

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Anyway, the HiperLCS2 appears to be implementing the "digital control" method shown
at 16:26 of the following video...
******* VIDEO ******
https://assets.infineon.com/is/content/infineon/coolmos-hard-commutation-stress-module-2

(This video is probably only find-able by typing "Infineon coolmos-hard-commutation-stress video" into
the google bar)

...So anyway, this method assures that you get no damaging reverse recovery at startup, when the magnetising
current of the transformer would otherwise have a DC offset and cause reverse recovery-type hard switching.

Page 7 of the HiperLCS2 datasheet explains how the HiperLCS2 can achieve resonant switching on the 2nd switching
edge.....this is pretty-much proof that they have done the "Infineon LLC control" method mentioned above. Do you agree?
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Is this product too good to be true?

What are its downfalls?, if any?

Strange that the datasheet depicts a selectable "centre frequency" for the LLC?
The IS pin connects to an auxiliary winding around the LLC transformer, so they are actually sensing what going on in the LLC transformer like this.

It says that the IS pin winding signals when the half cycle is over.....this seems an unusual way to do an LLC and they dont say why they have done this.
The IS pin winding (presumably) has the same number of turns as one of the secondary coils and is closely coupled to the primary coil.

It says that when the IS pin signal crosses over the CMP pin signal then the LLC power half cycle is over....but its not clear why that should be the case.

There also appears to be a bias winding from the LLC transformer which supplies the primary side controller.
Also, is there a maximum output capacitance, whereby, if fully loaded , and with above this maximum output capacitance at startup, then the LLC converter will never get up into regulation?
The primary side chip seems to have a few discrete levels of overcurrent protection, as opposed to certain other LLC controllers which allow you to more finely set the primary overcurrent level. So do you rate this as a disadvantage?
Can we just provide bias power to both of the chips by an external small "bias" power supply?
The HiperLCS2 datasheet on page 7 lists min/nom and max frequencies for the chip....must admit i prefer to set the min/max frequency accurately with a resistor or something, rather than be bound to values for them....so not so sure what's going on there.
If you watch the above video, it shows how the LLC may well suffer damaging reverse recovery during short circuit output.....does the HiperLCS2 have mitigations for this?
Page 33 of the HiperLCS2 datasheet show trr values of 200ns...which is only just inside the recomended maximum trr by infineon....also, pg 33 details a di/dt of 200A/us for the body diode in the HiperLCS2, but infineon says it requires 300A/us......so it is odd that such "marginal" devices appear to have been selected.

It makes you wonder why Power Integrations did not use GaN FETs inside the HiperLCS2....with an anti-parallel SiC diode...i mean, Power Integrations is no stranger to GaN ...their Innoswitch range uses GaN throughout.

Page 32 of the HiperLCS2 datasheet gives the overcurrent thresholds for the different HiperLCS2 chips....they are unfortunately in wide-apart levels, with no ability to select an "inbetween" current limit value. Also, its a struggle to find in the HiperLCS2 datasheet about what actually happens when the current limit gets breached...is it immediate shut down then restart...or does it increase frequency, or what?...its very important that we are told this, because short circuit is a time when damaging reverse recovery current can flow in the power stage and weaken, or blow up the LLC power stage......so can you tell what happens after a short circuit..and what measures have been taken to assure that no damaging reverse recovery will happen following a short circuit?

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So in summary, would like to know about the HiperLCS2...

1...What steps are taken to assure no damaging reverse recovery happens in the event of short circuit output?
2...Is there a limit to the amount of output capacitance that can be used?

3...Why were GaN FETs not used?, Power integraions is no stranger to GaN, and GaN FETs  with anti-parallel SiC diodes would have meant no damaging reverse recovery would ever happen.
4...Why hasn't this chipset overtaken the world yet?...if it does all that the datasheet promises, without significant problems, then
this chip should be taking over the world.

HiperLCS-2
https://www.power.com/sites/default/files/documents/hiperlcs-2_data_sheet_20250304.pdf?language=en