24W innoswitch CE flyback. Shielding the Innoswitch?

Hi treez,

Good day. Thank you for using Power Integrations solutions.

Comments to your inquiries are as follows:

• You are right; you may have internal copper layers running under the transformer, and the clearance/creepage consideration for internal layers is less depending on the standard we're considering. You may use the IPC-2221 calculation for the distance and width considerations.  

  From your statement, "What about going even further and completely shielding the innoswitch from the transformer by having layer 2 copper pour coming  right from primary to secondary side and layer 3 copper pour coming from secondary to primary side?"—as per our understanding, you would design layer 2 and layer 3 to have a copper pour in the whole PCB area; is this correct? If so, then it is not applicable since it may decrease the isolation between the primary and secondary sections.  

• Introducing a spark gap on your board prevents damage to the InnoSwitch device during Hipot testing, as the energy that would normally pass through the device will instead pass through the spark gap. However, this does not guarantee that your entire system will pass the Hipot test. Our InnoSwitch3-CE is tested to withstand Hipot testing up to 4 kV. However, the rest of the components in your design, including the transformer and Y-cap, must meet the safety clearance and creepage requirements to ensure proper performance. It is advisable to consult with your creepage and clearance safety engineer for guidance.

• Putting as spark gap on internal layer is not applicable since the functionality of a spark gap is introducing two conductors separated by a gap which allow an electric spark to pass between the conductors through air, and if it's in the inner layer then it won't allow a spark to pass because it is between insulators. 

• We won't be able to estimate the temperature the InnoSwitch device would rise to from the image on page 15 for we must consider a long list of variables of source pad PCB area, operating current, voltage, frequency, thermal resistance at the specific condition and including empirical once which can only be confirmed through test. Thank you for understanding. 

  I hope this resolves your inquiry. Should you require further clarification and support, please let us know. 
    

Thanks very much.
I notice that IPC2221A only gives general clearances and
not the clearances needed across the isolation barrier of
eg an offline flyback transformer. We wish to know the creepage distance required for inner layer copper across
the said isolation barrier?

Hi treez,

Thank you for your prompt response.

IPC-2221 also takes into account the working layer. You might find it helpful to look up an 'IPC-2221 Calculator' online—there are several open-source options available that you can use as a reference.

I hope this helps! If you have any questions or need further assistance, please don't hesitate to reach out.

Hi, the following thread appears to confirm that the hipot test voltage is higher due to the ringing between the common mode choke and the y cap. Please can you confirm this?

https://www.power.com/community/forum/ac-dc-conversion-forum/2024/esd-spark-gaps-across-innoswitch-and-common-mode-choke

So for example a 4kVrms  hipott test woudl normally peak at 5.6kV, but due to the Ycap/common mode choke interaction it will be significantly higher?

Hi treez,

Thank you for getting back to us.

The discussion did not mention the CMC and Y-Cap would induce high Hipot test voltage but discussed the functionality of the spark gap during an overvoltage event. The CMC and Y-cap do not induce voltage on the Hipot test.