RE: INNOSWITCH SMPS DESIGN REVIEW

Hi,

Could you please send images of top and bottom sides separately so that it is clearer to understand?

PI-AP

Hi,

Sorry for the delayed response.

Please find attached the TOP and the BOTTOM layer for PS mentioned above.

Kindly review at the earliest.

thanks and regards
Siddharth

Can someone please review the Pcb layout for the innoswitch

This is a bit urgent

Thanks and regards
Siddharth

Hi Siddharth,

The images you sent have both sides (top and bottom side) reference designators and footprints still visible so I am finding it difficult to interpret as many reference designators are not clearly visible or some are missing and so I have to guess and trace the component.

In the layout:

I don't see the FB connection to R7 which is the lower feedback resistor.
I don't see C11 connected to Vo.
I am guessing the locations of U$7 and U$4 as these names are not visible in the layout.
I don't see U$6.
I don't see a spark gap for ESD or surge protection.
Please make sure you also have the minimum creepage and clearance distance from primary to secondary if your transformer core is not covered with any insulating tape.

PI-AP

Hi PI-AP,

Thank you for your comments. I am sorry for the lack of visibility of the components. I am unable to attach the EAGLE files here.

I have incorporated all the changes mentioned

I don't see the FB connection to R7 which is the lower feedback resistor.

There was a problem in the NET. I have rectified it

I don't see C11 connected to Vo.

It is connected via TOP layer

I am guessing the locations of U$7 and U$4 as these names are not visible in the layout.

I have incorporated the names in the LAYOUT attached

I don't see U$6.

This is the Y cap, I have included the name in the layout attached

I don't see a spark gap for ESD or surge protection. I haave included this but is these a necessity? I have not seen this in one of the RDRs but have included a 1.5 mm width spark gap. Please refer the Layout attached

Please make sure you also have the minimum creepage and clearance distance from primary to secondary if your transformer core is not covered with any insulating tape.

I am Using POL-INN05 from Primer Magnetics

http://www.premiermag.com/pdf/pol-inn005.pdf

Anything else I need to to do?

Thanks and regards.

Siddharth

Usually the ESD spark gaps are 6.4 mm or 6.8 mm. The primary high voltage side to the secondary side creepage distance needs to be 8 mm or more if the transformer core is treated as primary and not covered with tape. These are recommended for safety, to make the ESD and sruge tests pass. RDR420 does follow these practices.

Hi,

I will surely rectify the spark gap distance.

The creepage is more than 8 mm. I have verified and would like you to have a glance
http://www.premiermag.com/pdf/pol-inn005.pdf
According to the datasheet the creepage distance has absolutely fine.

One more thing I want to confirm I am using track width of 24mil. I have taken into account 2A as maximum current and selected the track width(all though the current would never reach 2A)

Siddharth

Hi,

Just wanted to confirm what are you referring to exactly by track width? Are you referring to the trace width?

PI-AP

Hi,

Yes I am referring to trace width??? Is that OK??

Siddharth

Hi siddharthtaunk
I also try to start design a USB charger using INN2023.
But I can't find Eagle library.
Could you send me a link to this or did you do a library by yourself ?
Or if it's not a secret project can you send me sch and brd file ?
Thanks in advanced.