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low frequency oscillations at output

Posted by: bougnoul on

PI_Cohran

cld you pl  see issues posted on  low frequency oscillation with attahed oscillograms?

thnx

Comments

Submitted by PI-Terry on 08/15/2014

Hi,

 

I am sorry, I did not find the attached file. 

Submitted by bougnoul on 08/15/2014

i made them into pdf

Submitted by PI-Terry on 08/18/2014

Hi,

Thanks for attaching the files. I saw they are two waveforms that you attached, they looks difference between each other, the frequency of the first waveforms is about 1kHz, and the frequency of the second waveform is about 200Hz. Would you please let me know what are these waveforms? What is the difference between these two waveforms?  

Do you have the schematic, which IC you used to design your power supply?  

Submitted by bougnoul on 08/21/2014

can some PI expert look into my postings on the low frequency oscillation on the output? I mihgt have used wrong name to address the issue. ...but  of course, any PI tech person can do the favor.

thnx

-r

Submitted by PI-Terry on 08/26/2014

Hi,

 

Please check the reply on August 18th, would you please provide the information that I can further support you on this issue?

 

Thanks 

Submitted by bougnoul on 08/26/2014

Oh, I finally see  the email  from a week ago!The sch is still in the dashboard.The plots are on the output of the module: 270V input & 15V output, 1amp  non inductive load. See attached sch and output filter. Output has 497uF tantalum caps in application circuit.How to open 15v_filter.pdf.pdf: this  file has to be encrypted per Raytheon  IT security mandates.to open it, save it in a folder.rename the file from *pdf.pdf  to  *pdf.exedouble click on it. Enter exactly  text belowOutput filter for 15v modulethis filter uses almost 2uH leakage inductance with capacitors to reduce ripple noise to be less than 10mV.Since 2005, this has not been a problem. Older modules performed well.We suspect some parameters have changed that have  started causing such  output oscillations at very low frequencies. We need to substantially reduce this .Question from our customer is: why this is happening, how has it come about, what has changed & how do we fix it & prevent it from happening again.Any help will be appreciated.

I notice that the msg baord put everything in consecutive lines. I had created paragraphs for your convenience.

The passphrase for opening  the encrypted pdf file is again given below

Output filter for 15v module

hope the rest is clear in the previous msg

-b

Submitted by PI-Terry on 08/26/2014

Hi,

 

Thanks for addtional information. I followed your instruction, but I still can not figure out how to open the 15V filter file. Is it a file to show the out put filter, is it external filter? I can open the schematic, and I saw there is a post LC filter on the 15V output, it is basically a power supply using TOP244R, and the design looks good to me. Just to be sure that I have all the information that I can further assist you, the two waveforms that you attached about a week ago is the ouptu voltage ripple measured on the 15V output voltage at 1A load, the first one is with 500us/div, and the second one is with 2ms/div. They were recorded under the same conditions, right? Looks like there is a 166Hz low frequency / 130mV peak to peak voltage ripple and 1kHz 15mV peak to peak voltage ripple. So these two frequency is not either the line frequency or the jitter frequency, which is kind of strange, did you set up your probe and scope correctly, with AC coupling, 250Mhz bandwidth? 

From what you discribed, there was not issue from 2005, and now it becomes a issue. So to me, this issue is new, what is exact issue it caused? What is the change that you made which caused this issue? Any clue?   

 

 

Submitted by bougnoul on 08/27/2014

Terrythnx. I think you got the filter elements quite right so no need to figure out how to open the encrypted file.Besides, there is no indication that the low freq ripple is caused by the external filter.Also you stated the issue correctly. So, we have a clear common understanding of what is on hand.About instrumentation: yes, our set up is very dependable. There are 5 other modules in the VME chassis, all of them are characterized consistently & in the same manner as this 15V module. When there is no external DC load( i.e. a resistor), output of the 15v module always behaves in a stable manner with <10mV  broad  band "ripple" or noise..As you start adding resistive load, its behavior becomes erratic. On start up, it will be stable & oscilloscope trace shows 1 thing, after 10 minutes, it will be randomly different. After several hrs, yet again some other random  waveform...one of which is the scope picture I have presented.Now, what caused this change is exactly what we have to explore. Clearly, such oscillatory behavior comes from loop being not optimally compensated.  Our hunt is to find out how  to compensate better. I have to recall that in 2008-2009 time frame there used to be high  turn ON  overshoot for long duration(>10ms) which our system would catch & shutdown. There was also a long term drift of the output going to 18V( where Over voltage detection kicks in) after several 100 hrs of operation in field(in aircrafts)..when our system would  shut down. This was related to not having enough RC across the opto coupler feed at  “C”. This was increased to the extent possible because of size issues in the module. It is possible that  such high time constant totally upset phase margin thus leading to this behavior. It be noted that we do not know  when this low frequency oscillation started.  We changed RC values, saw no adverse effect during initial testing & accepted the results. I tried  to measure phase margin using Venable 350 system without getting any meaningful results & I reported that to PI.  It is possible the tendency of low frequency oscillation was there but did not surface until system went into field for long term operation.So bottom line is : given this situation, can you give any new knowledge about fixing this issue? I  hoping you have come across such response among the vast number of implementation & you becomes aware of  how such problems come about. You can draw from a large data base of knowledge to go in the right direction for a fix.Thnx-b

Hi,

Thanks for sharing the historical information, I am glad if I can help it out. To me, it looks like the issue starts to be raised after long term operation, which may relate to temperature parameters change. The difficulty here is to fully understand the issue and at what condition the issue comes out. This i still not so obvious to me or even to yourself as it is apprears to be random. Just make sure that there is no misunderstanding here, you mentioned the ripple voltage is less than 10mV without the resistor load. The ripple voltage becames higher when you added the resistor load, this should be normal as the ripple increased when the load current increase. Did I misunderstand it?

Based on you analysis, you think that the issue could be caused by the control loop which may not be optimized that can not reject the low frequency ripple because of low gain in the low frequency gain. I agree that this could be one of the reason. What is the difficulty that you have using Venable system to do the gain phase plot? Do you want help from us? If you do have difficulty on the real measurement, the other way to check how much of the phase or gain margin is to check the dynamic load response. You can refer to one of our applicaiton note about the control loop using Top Switch.

http://www.powerint.com/sites/default/files/product-docs/an57.pdf

 

Here is one comment from the schematic that I have: Usually we connect the R11 before the post filter L2/C9 to activate as a fast lane for the control loop. Hopefully this will give you a little hint...

Submitted by bougnoul on 08/28/2014

Terry

agree: R11 should have been at C13 cap. It is almost impossible to change that given config control we have. My reason for not making too much about it is that L is of little impact because of its low value hence does not add to phase shift on the sampled voltage to the feedback circuit.

I think the difficulty in getting proper loop response measured is the injection point. I had to cut trace from P4 to R11/R7, add 10 Ohms in between. Then run loop test like in any other converter. Unfortunately, the plot looked meaningless. I can redo it & email you again.

The "model" can give you pretty good phase calculations with a select set of values. Is the calculation dependable? Then I can rerun it & have model values installed. I do not think the values installed come from model.

thnx

-b

Submitted by PI-Terry on 09/02/2014

Hi,

 

I agree that the way you used to measure the loop gain and phase is very typical, I am not sure why you did not get the correct result. One of the way to check is to monitor the output voltage ripple, and inject the signal with some fixed frequency (for example 200Hz, 1kHz, 2kHz...ect), you should see the output ripple at this frequency on the output ripple if the setup is correct.The other way of measuring the loop gain and phase is to do current injection instead of the voltage injection, this method is introduced in the link the I attached in the last post. If you still get difficulty of getting the real loop and gain phase, the other way to check the stability is to do the transient load response, which indirectly give you the phase margin information too.  

To answer your question, the model introduced in the link is a pretty starting point of the analysing the loop gain and phase, you could also use our PI-expert software to help your design, you could actually get the open loop plot from the simulation of using PI-expert. Hope this is helpful for you. Thanks 

Tery

Finally, I can change to LINKSWITCH based design without opto coupler for the above design. I need to match the earlier design rating which was 15v@ 1amp. Input range is from 180V DC to 400V DC coming from a rectified 3phase.

PIExpert wont go beyond 500mA

How can I interleave 2 LINKSWITCHES?

Also, how can I add enable/disable function?

Submitted by bougnoul on 10/17/2014

 Seems interleaving will not be possible using LINKSWITCH.

Can I  instead parallel 2 such to get 15w, each deliverying 7.5w.  DO I need to synchronize them or just use std paralleling methods. Given that these are low power flyback, these outputs are "current sources".

Any ideas?

thnx

Submitted by PI-Terry on 10/20/2014

Hi,

 

Would you let me know which Lnk Switch that you are planning to use? With this power spec, I would recommend you to use the LinkSwitch HP product, that you do need to put power supply in parallel. Please find the production information as following:

 http://www.powerint.com/en/products/linkswitch-family/linkswitch-hp

 

Submitted by bougnoul on 10/21/2014

turns out, output current need not be more than 300mA with 15v.

This does not seem to be an issue with LNK626DG  as the model shows no red flags.

However,  I am not sure how I ought to ad an enable/disable circuit. At which pin can I add a MOSFET?

Submitted by PI-Terry on 10/27/2014

Hi,

 

Yes, if the output current is 300mA, you could use the LinkSwitch II products.

 

Unfortunately, there is no option to enable or disable the switching of LNK626DG. It does provide this option for LinkSwitch HP, that you can refer to the data sheet.

 

Thanks 

Submitted by bougnoul on 10/27/2014

LET ME LOOK INTO THE HP SERIES