Output switching noise.

Your schematic is good are layout is reasonable, and I guess your test methode is good. Would you like to try low esr capacitor or using mutiple capacitor in parallel? And PLs move the capacitors of the post stage output filters close to the terminal.

Thank you for the response, we will move to a low ESR Capacitor, and move them close to the output terminal.  We are goign to re-layout the board for a few reasons, are there any specific improvments you see we could make in the layout?

Thanks,

ryan

Your layout looks not bad. Always try your best to move  capacitors right behind  output diodes closer to the output diode and transformer, so the AC loop in the secondary side can be small, and move the capacitor of the post stage filter close to theoutput terminal to take care of the noise.

We re-did the layout, and I have attached the updated layout.

Also, I have attached 4 pictures, they are as followed.

Pic_1: Blue T1 Pins 1-4 & Yellow 24V otput(AC Coupled)

Pic_2: Blue T1 Pins 1-4 & Yellow 5V otput(AC Coupled)

Pic_3: Blue T2 Pins 1-3 & Yellow 5V otput(AC Coupled)

Pic_2: Blue T2 Pins 1-3 & Yellow 24V otput(AC Coupled)

What components can should we investigate to get the ringing off of the output.  It is causing big issues with our design.

Thank you,

Ryan

 Normally  the noise is cause by the ESR and ESL of the output cap. Since post stage inductors are use din your design, the ESR/ESL noise should be reduced significantly, and I think the noise is cause by your test. Waveforms of primary side and output ripple can not be monitored at the same time. And PLS  use the methode shown in our  DER/RDK report to test the ripple.  DER reports can be found via the following link:

http://www.powerint.com/en/design-support/reference-designs/design-examples/design-examples-archive.

regards

Thank you for the quick response,

  Those images, for the ourput side, were taken with the probe setup exactly as it is in those documents with the 2 capacitors in parrallel.  The input side measurements were taken with a high voltage differential probe.  

 We repeated the emasurements this morning, only doing one probe at a time, and the results are the same.  I can take more pictures, but it looks exactly the same.  Do you have any other recomendations?

Thank you,

Ryan

PLS make sure the Y cap connected between primary side and secondary side is good.  And the ampitude of  the pulse current to the secondary is very high for this high power design, and thus youcan try some ceramic cap at the output terminals to handle the noise. The ESR and ESL of the ceramic are much lower than aluminum cap, and hopefully the noise problem can be solved.

Should the ceramic caps be in parrallel with the Electrolitics, or in replace of them, or from power and ground  to chassis GND?

Thank you,

Ryan

Parallel the ceramic cap with the elctrolitcs.

we have tried the following:

Ceramic caps in parrallel with the output, and replacing the output caps with the following:

.1uf:

http://www.digikey.com/product-detail/en/K104K10X7RF5UH5/BC2665CT-ND/2356879

16V (replacement for the 100uf)

http://www.digikey.com/product-detail/en/SK330M016ST/338-2385-ND/1627455

http://www.digikey.com/product-detail/en/RR71C101MDN1/493-3716-ND/2207252

10V (replacement for the 100uf)

http://www.digikey.com/product-detail/en/SK470M010ST/338-1699-ND/1627491

http://www.digikey.com/product-detail/en/SK101M010ST/338-2370-ND/1627393

35V (replacement for the 100uf)

http://www.digikey.com/product-detail/en/SK330M035ST/338-1670-ND/1627457

http://www.digikey.com/product-detail/en/SEK470M035ST/338-2353-ND/1627209

http://www.digikey.com/product-detail/en/SEK101M035ST/338-2334-ND/1627119

There is no measurable change in our output noise.  

do you have any other recomendations, or specific things we can check to try and de-bug this problem.

Thank you,

Ryan

Based on the lnk from you, the ESR of these output caps are way too high.  For your application, the secondary current when primary switch turn off is huge, and thus huge voltage spike because of ESR/ESL and huge initial secondary current. .1uF ceramic means nothing for your application, because the resistance caused by the 0.1uF cap is dominated. ESR of ceramic cap can be around 2mohm, try ceramic cap with thousands uF to verify the issue can be solved first. And try your best to find some low ESR cap,( the ESR can be as low as 20-30 mohm,) and use several caps for each output.

 I believe the issue can be solved with low ESR/ESL cap.

regards